1. Technical Field
This invention relates to silicon transistors, and more particularly to a silicon transistor having a strained channel.
2. Description of the Related Art
Complementary metal-oxide-semiconductor (CMOS) technology is a dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has provided significant improvement in the speed performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced when CMOS devices are scaled into the sub-100 nm regime. An attractive approach for additional improvement of CMOS transistor performance exploits strain-induced band-structure modification and mobility enhancement to increase the transistor drive current. Enhanced electron and hole mobilities in silicon (Si) under biaxial tensile strain can be achieved. Enhanced electron and hole mobilities improve the drive currents of N-channel and P-channel MOSFETs, respectively. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, which can lead to chips that are up to 35 percent faster without having to further shrink the size of transistors.
Many designs of strained silicon layers for transistor fabrication utilize buffer layers or complex multi-layer structures on a bulk silicon substrate. Strained silicon substrate technology often utilizes a silicon-germanium (SiGe) graded buffer layer with a thickness in the order of a couple microns. A relaxed SiGe layer overlies the graded buffer layer. The relaxed SiGe layer has a larger natural lattice constant than that of silicon. Relaxed crystalline silicon is said to be lattice-mismatched with respect to relaxed crystalline SiGe due to the difference in their lattice constants. The mismatch is small, which permits silicon to be grown as a single crystal aligned with the single crystal structure of SiGe. As a result, a thin layer of silicon that is epitaxially grown on the relaxed SiGe layer will be under biaxial tensile strain because the lattice of the thin layer of silicon is forced to align to the lattice of the relaxed crystalline SiGe layer, as illustrated in FIGS. 1A and 1B. Transistors fabricated on the strained silicon layer will have enhanced electrical performance.
As shown in FIG. 1A, relaxed SiGe has a lattice structure slightly larger than relaxed silicon. When pure silicon is formed as a single crystal to match the lattice structure of relaxed SiGe, the silicon is under biaxial tension, as shown in FIG. 1B. This is well known in the art and explained in detail in U.S. Pat. No. 7,208,754 incorporated herein by reference. This physical property of silicon being held under biaxial tension can be used to provide various advantages, as explained herein.
Various other techniques have been attempted to form electrically isolated transistors. Such techniques are described in U.S. Pat. Nos. 6,902,965; 7,436,005; and 7,229,867, each of which are incorporated herein by reference.